One type of synchronous memory device architecture includes several memory arrays that are activated in banks during a memory access. In this type of synchronous memory device, a bank clock is typically used to activate the clocking mechanism of a column path in a bank that is being accessed. FIG. 1 is a timing diagram illustrative of a conventional data clocking system for a memory device having a multiple column address strobe (CAS) latency design. More particularly, FIG. 1 shows the timing for a CAS latency two (CL2) and a CAS latency three (CL3) operational mode.
Waveforms 10-15 of FIG. 1, respectively, represent an external clock signal CLK, a bank clock signal BNKCLK, a data line clock signal DL2CLK, an input/output clock signal IOCLK, an output circuit clock signal OCLK and a data signal DQ during the CL2 mode. Similarly, waveforms 10'-15' represent clock signal CLK, signal BNKCLK, signal DL2CLK, signal IOCLK, signal OCLK and signal DQ during the CL3 mode. In both the CL2 and CL3 modes, the leading edges of signal CLK trigger leading edges in signals BNKCLK and OCLK. For example, leading edge 10.sub.1 (and 10.sub.1 ') of signal CLK causes leading edges 11.sub.1 (and 11.sub.1 ') in signal BNKCLK and leading edges 14.sub.1 (and 14.sub.1 ') in signal OCLK. In addition, leading edges 11.sub.1 and 11.sub.1 ' of signal BNKCLK, in turn, respectively trigger leading edges 12.sub.1 and 12.sub.1 ' of signal DL2CLK.
Then, in a first cycle (i.e., cycle 1) of CL2 mode operation, leading edge 12.sub.1 of signal DL2CLK causes a leading edge 13.sub.1 in signal IOCLK. The timing of signal IOCLK is determined so as to achieve a time margin t.sub.m between a falling edge 13.sub.2 of signal IOCLK and a leading edge 14.sub.2 of signal OCLK in the next cycle (i.e., cycle 2). The timing of signal OCLK is carefully designed for proper operation. Signal OCLK is used to output data onto an output bus (not shown) that is captured from data lines (not shown) that were restored (or equilibrated) by signal IOCLK. Thus, the timing of signal OCLK is adjusted so that the signal on the data lines has time to be driven to the proper levels before signal OCLK causes the data lines to be sensed. Thus, delaying signal OCLK allows more time to sense the data lines during a current cycle, but at the cost of increasing t.sub.AC (access time) from the next rising edge of signal CLK. In practice, the timing of signal OCLK is adjusted during the design process so as to achieve an optimal trade off in view of the layout, loading, process variations of the semiconductor materials, etc.
However, adjusting the timing of signal OCLK to optimize the CL2 mode may adversely affect performance in the CL3 operational mode for the following reasons. As in the CL2 mode, a rising edge of signal DL2CLK triggers or fires signal IOCLK. However, in the CL3 mode, the firing of signal IOCLK is pushed into the next cycle (in the CL2 mode, signal DL2CLK fires signal IOCLK in the same cycle), as shown by leading edge 13.sub.1 ' in FIG. 1. More specifically, in the CL3 mode, two cycles are used to drive the data onto the Data lines (not shown), which are then sampled and driven onto the output bus (not shown) in the third cycle in response to the firing of signal OCLK. Consequently, within the third cycle of a given read operation, signal OCLK must be fired before signal IOCLK is fired so that the Data lines (not shown) will be sampled and driven onto the output bus (not shown) before signal IOCLK restores the Data lines in preparation of receiving the IO-data of the next read operation. As a result, if the timing of signal OCLK is changed so that an OCLK pulse overlaps with an IOCLK pulse, the read operation may not generate the proper data. In view of the above discussion, there is a need for a data clocking system that can adjust the timing of signal OCLK to optimize each CAS latency mode while ensuring that within a given cycle, signal OCLK is fired before signal IOCLK is fired so that the OCLK and IOCLK pulses do not overlap.